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EE 402 VLSI II: System-on-Chip (SoC) Application Specific Integrated Circuits (ASIC) built on RISC-V Architecture Select Term:
1. Introduction - System-on-Chip (SoC) concept (1 week) 2. RISC-V overview (2 weeks) 3. On-chip interconnect, interfacing to RISC-V core, bus protocols (2 weeks) 4. Communicating with peripherals 5. Memory selection/configuration/compilation and interfacing (1 week) 6. Extensions to RISC-V core, adding custom hardware and integrate it with RISC-V core, memory and peripherals (2 weeks) 7. Floorplanning of SoC ASIC 8. Power planning of SoC ASIC 9. Cell placement of SoC ASIC 10. Clock tree synthesis of SoC ASIC 11. Routing of SoC ASIC 12. Finishing of SoC ASIC 13. Verification / Sign-off of SoC ASIC
SU Credits : 3.000
ECTS Credit : 6.000
Prerequisite : Undergraduate level EE 401 Minimum Grade of D OR Undergraduate level EL 401 Minimum Grade of D
Corequisite : EE 402R
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