MSc.Thesis Defense:Umut Barut

Development of Process, Voltage and Temperature Variation Aware Highly Energy-Efficient Deep Neural Networks with High Inference Accuracy for Internet-of-Things Applications

Umut Barut
Electronics Engineering, MSc. Thesis, 2024

Thesis Jury

Asst. Prof. Ömer Ceylan (Thesis Advisor)

Prof. Yaşar Gürbüz

Asst. Prof. Atilla Uygur

Date & Time: 24th, 2024 – 9.00 AM

Place: FENS G025

Zoom Link: https://sabanciuniv.zoom.us/j/7537126555?pwd=aTBLOStmL3VOckg3Q0Rkc0tZTXR5UT09

Keywords : internet-of-things, deep neural network accelerator, energy efficiency, edge computing, probabilistic timing error model, PVT variation aware voltage underscaling

Abstract

In today’s world, the widespread usage of the internet generates vast amounts of data. With advancements in hardware and algorithms, artificial intelligence (AI) models have significantly improved, leveraging high-speed hardware to process large datasets. These models are now integral to various daily applications. The Internet of Things (IOT) further simplifies data collection, processing, and response actions, enhancing the popularity of AI applications on IoT devices. However, this creates challenges such as internet bandwidth overhead, increased latency, and vulnerability to cyber-attacks. To address these issues, edge computing capabilities are essential. Deep neural network (DNN) applications, which require extensive multiply and accumulate (MAC) operations, demand fast and energy-efficient hardware. Application-specific integrated circuit (ASIC) DNN accelerators are a potential solution for IoT devices. To further enhance energy efficiency, voltage reduction on power supplies is a viable method, despite causing timing errors that DNNs might tolerate due to their inherent nature. Extensive MAC operations also lead to significant switching activity, potentially generating noise on the chip’s power lines. In this thesis, process voltage temperature (PVT) aware model is developed and demonstrated to finding error probability due to voltage and temperature noise. A 16x16 systolic MAC array accelerator was designed using 65nm CMOS technology to verify the model. Single MAC unit is analyzed for timing error probability and result is compared with Monte Carlo (MC) simulations. Developed model and MC simulation error probability are slightly different. Nonetheless, the model demonstrated decent accuracy and was approximately 826 times faster than MC simulations, allowing for rapid observation of voltage reduction effects on the accelerator in terms of timing error probability.